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 SMTS - IC Packaging Engineer (Board Level-Reliability&AssemblyDevelopment)

Details
Country: USA
Location: California-Silicon Valley/San Jose SUNNYVALE, CA 94086
Total applied: 39
Job Category:Engineering
Relevant Work Experience:5+ to 7 Years
Education Level:Bachelor's Degree
Location:SUNNYVALE, CA 94086
Status:Full Time
Occupations:General/Other: Engineering
Career Level:Experienced (Non-Manager)
Relevant Work Experience:5+ to 7 Years
SMTS - IC Packaging Engineer (Board Level-Reliability&AssemblyDevelopment)

Candidate will be the internal lead for all board level reliability testing and development for Maxim IC packages. Work closely with all new package development projects for their board level development and testing. Manage projects from concept through development, qualification to production.

Responsibilities: Responsible for setting up and managing all aspect of a board level assembly and reliability test laboratory within Maxim. Responsible for defining board level test criteria based on materials, design and industry roadmaps. Participate in material selection and qualifications to ensure product performance, reliability and cost targets are met. Determines failure mechanisms related to materials and processes utilizing analytical techniques, statistical modeling and/or FEA modeling. Define and generate relevant board design rule for customers for all Maxim products. Interface with our top ten key customers on technology roadmaps Write technical reports on research and development activities, process and materials specifications, and application notes as needed. Update peers and management on progress. Provide guidance during technology transfer to manufacturing engineering at production facilities.

BS/MS in Material/ Mechanical/ Electronics Engineering Minimum 5-8 years' experience in Advanced (e.g Flip Chip, uCSP, WLP, QFN) board level assembly Knowledge of SMT process, and material characteristics especially related to the second level reliability impact Knowledge of statistical tools, DOE, SPC, FMEA and 8D methodology

 

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