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 SMTS - IC Packaging Engineer (Wire Bond Development)

Details
Country: USA
Location: California-Silicon Valley/San Jose SUNNYVALE, CA 94086
Total applied: 33
Job Category:Engineering
Relevant Work Experience:5+ to 7 Years
Education Level:Bachelor's Degree
Location:SUNNYVALE, CA 94086
Status:Full Time
Occupations:General/Other: Engineering
Career Level:Experienced (Non-Manager)
Relevant Work Experience:5+ to 7 Years
SMTS - IC Packaging Engineer (Wire Bond Development)

Candidate will be the project lead for wire-bonded (Copper and Gold) IC package process development and design methodology development at Maxim Integrated Products. Work closely with multiple business/design units and manufacturing facilities to develop and implement the project plan. Manage projects from concept through development, qualification to production.

Responsibilities: Copper and Gold wire bonding process technology development and implementation.  Evaluate the quality and robustness of silicon from different fab locations and technologies. Design, characterize and qualify copper and low-K dielectric silicon technologies. Define, characterize and implement bond pad pitch reduction, stagger bond pad and CUP (circuits under pad) designs. Work with subcons to push the wire bond capability in terms of wire length, multiple rows to tier connections and diameter reduction. Generate relevant assembly design rules, and process windows. Participate in supplier selection processes and material qualifications to ensure product performance, reliability and cost targets are met. Determines failure mechanisms related to materials and processes utilizing analytical techniques and/or FEA modeling. Write technical reports on research and development activities, process and materials specifications, and application notes as needed. Update peers and management on progress. Provides guidance during technology transfer to manufacturing engineering at production facilities. Provides guidance during technology transfer to manufacturing engineering at production facilities.

BS/MS in Material/ Mechanical/ Electronics Engineering Minimum 6-8 years' semiconductor packaging experience (gold/ copper wire bond process development preferred). Knowledge of DOE, SPC, FMEA and 8D methodology Travel is required to Southeast Asia.

 

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