Analog/Mixed Signal IC layout Engineer

Job Description:
In this position, you will play an important role in generating layout for analog and mixed signal IC design and CMOS image products. The candidate should work closely with design team to conduct the physical implementation (layout), LVS/DRC layout verification, and chip floor planning. You will also be responsible for layout optimization, error debugging, and post layout extraction. The candidate should be expected to work with other designers and layout engineers to achieve the full chip integration, place and route, chip top level verification, and tape out.

Responsibilities:
* Take active role in physical layout for high performance ICs with analog, mixed-signal, digital, and image sensor array on a single die
* Conduct layout vs. schematics check and design rule verification on both block level and chip level
* Debug and analyze all the errors during layout and verification

* Work with design engineer to generate top level chip floor planning
* Help design engineer to optimize layout design for achieving best performance

* Make best matching layout for both active device and passive element
* Follow the instruction from design engineer and work closely with other layout engineers to make the full chip integration

* Provide post layout extraction for parasitic analysis and full load simulation

Education Requirement:
*BS in Electrical Engineering

Candidate Profile:
* Over 2 years of layout experience for analog and mixed signal IC design

* Must have a solid understanding of design rules and verification for sub-micron CMOS processes, experience with sub-micron CMOS SOI process is a plus
* Proficient in device matching, parasitic analysis, current density, and isolation techniques

* Experience with floor planning and chip top level integration
* Good knowledge on latch up, guard rings, metal density, metal shield and antenna rules

* Experiences with Cadence and other CAD tools including Virtuoso Schematics Editor, Analog Artist, Spectre/Hspice simulator, Virtuoso layout, layout XL Editor, Diva/Dracula/Assura/Calibre layout verification tools

* Experience with place & route flow and tape out procedure is a plus

* Basic knowledge on semiconductor technology

* Experience with debugging and/or writing DRC and LVS decks is a plus

* Self motivated with good communication skills.

* Positive attitude to work with other design and layout engineers
* Take high level of responsibility and dedication to your design