Staff Design Engineer

Innovation. Excellence. Integrity. Not just abstract concepts at LSI Corporation, but the way we conduct business with customers, partners, and key stakeholders. Add individual responsibility to the mix and you have the recipe for a dynamic environment, technological achievement, challenging career opportunities, and the potential for personal growth. Employees at LSI understand that they are helping to shape the future of technology in the storage and consumer markets. That’s why we’re always looking for the best and the brightest to join our winning team. Position Description:The Packaging Technology group offers a breadth of opportunities spanning IO ring physical implementation for customer designs, developing new IC related packaging technologies, and IP co-design. Responsibilities include the following.• IO ring implementation for LSI ASICs and ASSPsIn this capacity the candidate will create IO rings, bump and pad patterns, aspects of the chip-level power mesh including early verification, and assess trade-offs between IC and package substrate design constraints.The position will require customer discussion, and close interaction with package designers, IC teams, and IP development groups. Tools used include Synopsys, Magma, Calibre, power analysis and extraction tools, viewing of Cadence APD MCM files.• Technology DevelopmentThe team responsibilities include the creation of new IO placement schemes, definition of requirements and solutions for each new technology node in areas relating to packaging, and evolving new packaging techniques such a multi-chip-packaging as they relate to the IC.• IO and IP Co-DesignThe candidate will be required to work with IO and IP development teams to derive optimal bump and pad placement positions, provide recommendations on IO and IP aspect ratios, necessary pin locations and layers required for packaging, and conduct feasibility studies with package designers.• Design FlowThe candidate will at times be required to work on design flow integration, including development of point tools and/or scripts to assist in the process of package co-design, and ensuring inputs and outputs to the packaging flow integrate within the overall design system. Point solutions developed will be used predominately for the team's internal purposes.Bachelors or higher degree in Electrical Engineering or related field. Knowledge of physical layout, verilog netlist syntax, basic principles surrounding IO placement, and an understanding of a typical ASIC design flow is required. Experience of Synopsys, Magma, Calibre, and APD tools preferred. Candidate should be proficient in the use of UNIX and should be able to develop scripts in a mix of TCL, Python and csh as required. An understanding of IO circuit and signal integrity concepts is highly desired. To Apply Visit LSI CorporationQualifications:Bachelors or higher degree in Electrical Engineering or related field. Knowledge of physical layout, verilog netlist syntax, basic principles surrounding IO placement, and an understanding of a typical ASIC design flow is required. Experience of Synopsys, Magma, Calibre, and APD tools preferred. Candidate should be proficient in the use of UNIX and should be able to develop scripts in a mix of TCL, Python and csh as required. An understanding of IO circuit and signal integrity concepts is highly desired.