ASIC Design Engineer:

Innovation. Excellence. Integrity. Not just abstract concepts at LSI Corporation, but the way we conduct business with customers, partners, and key stakeholders. Add individual responsibility to the mix and you have the recipe for a dynamic environment, technological achievement, challenging career opportunities, and the potential for personal growth. Employees at LSI understand that they are helping to shape the future of technology in the storage and consumer markets. That’s why we’re always looking for the best and the brightest to join our winning team. Position Description:Position Description:A qualified applicant for this position would be responsible for the SoC development, Timing closure using STA, Code writing, Channel, ECC and other IP like ARM, DDR, SATA-PHY integration, documentation and verification and customer support. This position also requires a close working relationship with the internal SoC development team, Physical Design, IP design team, Test Engineering as well as customerResponsibilities:Responsibilities include developing SoC for HDD application including timing closure, developing top level constraints, synthesis, formal verification, gate level sim using SDF, developing ATE vectors and test mode supports. A comprehensive verification environment and test suite must be developed and maintained to support the development activity and to facilitate the verification of the IP in the SoC. Thorough documentation is to be developed including a users guide for HDC and top level datasheets describing the IO and the relevant timing relationships between the other IP like SATA, RC, ARM etcResponsibilities also include customer support. To Apply Visit LSI CorporationQualifications:Required Education:A minimum of a MSEE and 5+ years of experience relevant industries experience.Required Skills:Experience with SoC EDA tools used in synthesis, simulation, static timing analysis, test insertion, Floor Planning, I/O ring design and ATPG, and formal verification to support customerExperience in domain knowledge regarding low power, highly area optimized, low cost HDD Controller (HDC) for consumer market as well as logic design and verificationExperience in developing verification test benches for various test modes to verify IP at SoC levSupport customer for SoC development and Read Channel integration.Knowledge of Verilog design languages, (VHDL a plus)Excellent technical troubleshooting and demonstrated problem solving skillsLeadership quality and can provide mentorship to Jr. DesignerWillingness to work in highly visible and dynamic environmentExperience with C code language as well as pearls and Awk a plus