ASIC Verification Engineer

Job Description
Wireless LAN MAC and system interface verification. The candidate will be responsible for unit and chip-level verification of WLAN MAC and interfaces. He/she will develop test strategy and test plan that achieves the project's verification goals. He/she will execute the plan by building and maintaining testbenches, and develop tests. He/she will measure verification success by functional and structural coverages.

Skills/Experience
Experienced in RTL/Behavioral modeling in Verilog
EDA Simulation tools (VCS,NCSIM)
Working knowledge of creating testplan, building testbenches using Vera / RVM, creating test-suites based on micro-architecture spec and functional spec
Knowledge of formal verification is a plus
Ability to debug design in simulation platform
Experienced with Scripting languages like PERL/PYTHON and other software languages including C/C++
Experienced in Verification of Layer 2 (Ethernet/WLAN) networking and high speed I/O protocols
Detailed and team oriented
Good verbal and written communication skills
Good people skills/Team builder

Additional Skills

Education Requirements
Bachelor's degree with at least five years of Design Verification experience or Master's degree with at least three years of Design Verification experience.

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