Design Engineer

Innovation. Excellence. Integrity. Not just abstract concepts at LSI Corporation, but the way we conduct business with customers, partners, and key stakeholders. Add individual responsibility to the mix and you have the recipe for a dynamic environment, technological achievement, challenging career opportunities, and the potential for personal growth. Employees at LSI understand that they are helping to shape the future of technology in the storage and consumer markets. That’s why we’re always looking for the best and the brightest to join our winning team. Position Description:Position Description:A qualified applicant for this position would be responsible for the development and support of verification test bench and test cases for mixed signals IP used in SoC and/or ASIC for hard disk drive applications. Also need to develop synopsys (DC & Primetime) models as well as functional verilog model to support SoC level synthesis, STA analysis and top-level verification. The position requires a close working relationship with the core IP development, SoC design, Customer and IC test engineering teams.Responsibilities:Responsibilities include developing a comprehensive verification environment and test suite and maintained to support the development activity and to facilitate the verification of the IP in the SoC. Verilog RTL and gate level timing-annotatable simulation models must be developed and need to performed logic synthesis (DC) and timing analysis (Primetime), and generating and maintaining timing information (SDF) for these models.. Thorough SoC centric integration documentation is to be developed including a users guide for the IP and top-level datasheets describing the IO and the relevant timing relationships between the IO. Need to ensure testability of this IP at SoC level and need to develop functional test pattern, which can be used in manufacturing environment. To Apply Visit LSI CorporationQualifications:Required Education:A minimum of MSEE and 3 + years of experience.Required Skills:Experience in verification, synthesis and static timing analysis.Experience with SoC/ASIC EDA tools used in synthesis, functional verification, static timing analysis, gate level simulation and formal verificationExperience in developing verification test benches and test cases.Knowledge of Verilog design languages, (VHDL a plus)Excellent technical troubleshooting and demonstrated problem solving skillsSuperior written and verbal communication skillsWillingness to work in highly visible and dynamic environmentHard Disk Drive IC design experience is a plusFamiliarity with design concepts and architectures for complex digital signal processing functions including data conversion, PLL's (Phase-Locked Loops), clock generators, frequency synthesizers, clock and data recovery circuits, and high-speed transceivers is a plusExperience with C code language a plus