Engineer, Design for Test (DFT)

Marvell. Moving Forward Faster.Marvell offers revolutionary devices that touch every point of the communications infrastructure: switching, transceivers, wireless, PC connectivity, communications controllers, and storage. Our continuous cycle of innovations has enabled Marvell to consistently deliver the industry’s gold standard, emerging as the market leader in virtually all of our product categories.

Position Description:

Participate in design, verification & debug of highly integrated SOC designs for wireless networking applications, with particular emphasis on entire DFT strategy. Includes design & verification of dedicated DFT components, usage of DFT tools such as ATPG & BIST, pattern generation and silicon debug. Good communicationskills needed as the candidate is required to work closely with other design engineers within the group & also external groups such as CAD, test engineering and product engineering.

To Apply Visit Marvell Semiconductor

Qualifications:

BS EE with 4+ years experience of deep submicron SOC design and verification. Analytical problem solving a must, together with good knowledge and familiarity of full ASIC design flow and DFTspecific tools/techniques. Both written & verbal communication skills important.