Failure Analysis Engineer, Senior

National Semiconductor – Senior Failure Analysis Engineer (Santa Clara)

 

National Semiconductor, the industry's premier analog company, creates high performance analog devices and subsystems.  National's leading-edge products include power management circuits, display drivers, audio and operational amplifiers, communication interface products and data conversion solutions. National's key analog markets include wireless handsets, displays and a variety of broad electronics markets, including medical, automotive, industrial, and test and measurement applications. Headquartered in Santa Clara, California, National reported sales of $1.93 billion for its most recent fiscal year. 

The Santa Clara Central Analytical Services Group is committed to supporting National Semiconductor strategic imperatives in the areas of New Product Qualification, Best in Class Failure Analysis and Service Lab Cycle Time Reduction for delivery of highest value solutions providing a competitive advantage to our customers. 

The group is currently seeking a Senior Failure Analysis Engineer who will be responsible for all aspects of releasing and sustaining products to manufacturing. This includes, but is not limited to, failure analysis, yield enhancement and test methods. The Engineer acts as a central resource for all product FA and yield issues, and interfaces with other engineering groups including Design, Process, Test, Marketing, and QA/Reliability.

Key Areas of Responsibility:

§ The candidate must have experience with analog and digital circuit debug.

§ Must be capable of de-bugging op-amp amplifier designs, using knowledge of Bi-polar and Bi-CMOS processes, as well as CMOS random logic and CMOS memory devices (SRAM, DRAM).

§ Proficient with parametric analyzer, curve tracer, oscilloscope, power supplies and microscopes.

§ Microprobing and Nano-probing for root cause determination and failure verification.

§ Ability to setup design and layout databases from Cadence and Knights vendor.

§ Experience with failure analysis techniques such as Emission Microscopy, TIVA, OBIRCH, SEM technology and Acoustic Microscopy.

§ Familiar with testing methodology from testers like Catalyst, IMS and Teradyne.

§ Breadboard simple circuits for application debug.

§ Capable of performing mechanical x-section and parallel-lap.

§ Ability to demonstrate wet chemistry deprocessing techniques.

§ Must be familiar with Reliability stress test such as: DOPL, THBT, ACLV, TMCL, etc.

Requirements:

Education: MSEE

Experience: 3+ years of relevant work experience.

 

As an equal opportunity employer, National Semiconductor encourages and supports a diverse workplace.

 

Send resumes to:  bdegsc@nsc.com Education: Masters Degree (18 years)Job Level: Professional/Individual Contributor