Place and Route Engineer, Sr.- (Silicon Valley)

Job Description
Opportunities for exceptional IC physical design engineer (automatic placement and route) to implement complex RF/Mixed-IC/digital designs for wireless applications in state-of-the-art deep submicron technologies using the latest EDA tools and methodologies. Responsibilities include full chip floor-planning and partitioning, physical synthesis, place and route, clock tree synthesis, power and signal integrity analysis and timing closure. Involves tasks in both implementation and development/automation of tasks for full chip physical design in addition to new methodology development and vendor tool evaluations and integration. Work is in a dynamic team environment with aggressive schedule, chip power consumption and area targets

Skills/Experience
Candidates preferably have 5+ years of relevant experience
Must have a strong physical design background and should have participated in implementation of SOC designs in DSM technologies using latest Synopsys, Cadence and/or Magma PD toolsets
Technical depth in the areas of synthesis, floor-planning, placement and route, timing closure and/or electrical analysis is a must
Must be able to work independently and interface with various groups and vendors
Project leadership experience and skills will be an advantage

Additional Skills
Experience in developing ASIC design & implementation flows
Scripting skills in perl and tcl will be a plus

Education Requirements
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering

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