SSI_Physical Design Staff Engineer

Position Summary


Samsung Semiconductor Inc, the one of the world’s largest semiconductor manufactures is putting together an elite team of Design Engineers to work on the next generation of Mobile Media System-on-Chip applications. This cutting edge technology will be used in M3P Plays, Phones and other mobile devices.
We are currently looking to fill several System-on-Chip Engineering positions in our San Jose office to support one of the top tier customers in the Silicon Valley, as well as our growing System LSI business.


Common Essential Duties & Resp.


This position will be responsible for physical design activities from netlist to complete GDS in large, very low-power SoC designs in 65nm or smaller process technologies. The SoC designs typically include various hardened processor and mixed signal IP blocks and high speed IO interface PHYs. Major responsibilities will include:
– Layout early engagement including hierarchical partitioning, floor planning and SDC clean-up
– Hierarchical and timing driven place-and-route
– Parasitic extraction
– Power integrity, clocking integrity, and signal integrity analysis
– DRC/LVS


Background/Experience


– Hands-on experience in physical design of large SoC’s
– Extensive experience in clock and power implementation methodologies and practices in low power designs
– Deep understanding of hierarchical/timing driven layout methodologies and practices
– Experience with integrating various type of hardened IP modules
– Ability to collaborate with RTL, synthesis, STA engineers in timing closure, gate level verification and debug
– Familiarity with various ECO flows and techniques
– Good communication skills
– 7+ years physical design experience with 3+ Year experience in Synopsys and/or Magma physical design tool suites
– BSEE required, MSEE preferred
To Apply for this position, please CLICK HERE