Staff Logic Design Engineer

Marvell. Moving Forward Faster.Marvell offers revolutionary devices that touch every point of the communications infrastructure: switching, transceivers, wireless, PC connectivity, communications controllers, and storage. Our continuous cycle of innovations has enabled Marvell to consistently deliver the industry’s gold standard, emerging as the market leader in virtually all of our product categories.

Position Description:

Architect and implement verification IP for Ethernetswitches, routers, and SOC products.Develop transactors, scoreboards, functional coveragemodels, constrained random test methods, and assertions.Evaluate, adopt and propagate new tools and methodologies.

To Apply Visit Marvell Semiconductor

Qualifications:

Required: 1. Masters or PhD; EE or CS 2. 5+ years experience 3. Strong knowledge of Verilog, Perl, and at least one high level verification language (SystemVerilog, Vera, Specman). 4. Solid understanding of object-oriented programming. 5. Experience with constrained random stimulus generation and advanced self-checking structures (scoreboarding). 6. Familiarity with layers 1-3 networking protocols. Preferred: 1. SystemVerilog, C++, Synopsys VMM 2. Experience creating test plans, designing functional coverage models, and writing assertions. 3. Familiarity with design patterns.