DFT Engineer

As a member of the DFT/Test Methodology team, you'll be working with a highly skilled and motivated group of engineers whose primary goal and focus is to deliver high-caliber Test Methodologies to increase yield and diagnosis while decreasing the overall cost of testing very complex custom ASIC designs.


You'll be supporting the Test Methodology team in the development of complex DFT strategies to attack the test issues that arise from testing enterprise networking, and complex CPU chipset ASICs.

The Test Methodology team at Client is strongly linked to industry standards and techniques to battle many of the problems that arise with the ever-shrinking geographies of complex ASIC design, and you'll have the opportunity to be an integral part of this team.

Must have US work authorization

 

Required:

- A Bachelors Degree or Masters Degree in Electrical Engineering or the equivalent

- Minimum 2 years of experience in chip design or DFT

- The ability to work in a multi-disciplined, cross-department environment

- Solid experience in analog and digital circuit design, and device physics

- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

- Experience in Verilog coding

- Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

- Excellent problem solving, debug and communication skills



Prefer:
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Logic BIST design and debug experience
- Well-versed in ATPG vector generation, simulation, debug.