Senior DFT engineer and ASIC Engineers

We are looking for a candidate with experience in-

Senior DFT EngineerMinimum 4 years of experience in chip verification or DFT Strong DFT background (DFT, ATPG and Scan, BIST, and others) Experience in Verilog coding Good understanding of Si processing, logical and physical synthesis Experience in Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.) Boundary Scan experience using Scanworks Well-versed in ATPG vector generation, simulation, debug. Knowledge in Verilog and PERL .

 

ASIC Verification Engineers (5 positions)

-Minimum 5+ Years of experience in Verification of ASIC/SOC/FPGA

-Test plan development, Testbench development, test case development & debugging

-Experience in Verilog, System Verilog or Specman or  VERA or C++ based verification

-Good knowledge of Protocols like Ethernet, SAS, SATA, PCI Express, AMBA, USB etc.

-Scripting Languages like Perl or tcl

 

ASIC Design Engineers (5 positions)

-Minimum of 5 years of experience in Verilog/VHDL design, synthesis, and verification

-Experience in system integration on both FPGA and ASIC platforms.

-Experience with Verilog, VCS, Modelsim, Synopsys DC, DFT tools, and logic synthesis tools.

-Experience in using Formality/Primetime/Spyglass

-Strong programming skills in scripting

 

ASIC Physical Design Lead Engineer (5 positions)

-5+ years of back-end experience including tape-out in 90nm technology or below.

-Experience in Floor planning, place and route, and clock tree synthesis.

-Experience in power grid, power analysis and optimization.

-Experience in Extraction, back annotation, plus signal integrity based timing analysis and closure.

-LVS / DRC background is a must.

-Hands on experience with Magma, Synopsys and/or Cadence back end tools.

-Proficiency in script writing: Perl, tcl, make, Linux/Unix shell script.

-Proficiency in analyzing reports from back end tools.