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Staff Verification Engineer (F9-13) San Jose, CA
| Details |
Country: USA
Location: California-Silicon Valley/San Jose San Jose, CA 95138
Total applied: 27 Job Category:Engineering
Relevant Work Experience:5+ to 7 Years
Education Level:Bachelor's Degree
Location:San Jose, CA 95138
Status:Full Time, Employee
Occupations:General/Other: Engineering
Career Level:Experienced (Non-Manager)
Relevant Work Experience:5+ to 7 Years
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Staff Verification Engineer (F9-13) San Jose, CA
Staff Verification Engineer (F9-13)
As diverse technologies that span the consumer, communications, and computing markets begin to converge, changing the digital media landscape, our flexibility and ease-of-use are increasingly driving the user experience. At IDT, we are proud of our 27 years of living and thriving in our ever changing environment. We are bringing together a team of remarkably talented and insightful people to explore the opportunities that the digital media explosion creates, with a focus on mixed signal semiconductor solutions. We are enabling advances in download time, power efficiency, processing speed, quality and reliability, while lowering costs and speeding time-to-market for our customers. This is the place to be.
Responsibilities
Excellent knowledge of vera/SystemVerilog and Verilog. In addition, the candidate should have rich experience in OOP programming techniques and scripting languages (Perl). Excellent oral/written communication skills are a must. Good knowledge and experience in PCI or PCI Express shall be a plus.
Participate in the design and verification of industry-leading high-end switches. Create Vera/SystemVerilog test benches and test cases for hardware verification of systems, boards, and ASICs. Identify test bench requirements. Create test benches specifications, and hold reviews. Create test benches (Vera). Create test cases and help run simulations to debug and verify design is correct. Train other engineers to create and run test cases. As required, help reproduce system hardware anomalies in verification environment.
Requirements
Requires a BSEE with 5-12 years of experience; MSEE is preferred. Excellent knowledge of digital design and simulation techniques, including HVLs (vera/System Verilog) and Verilog. The candidate may also have a good deal of knowledge and experience in the following protocols: PCI, PCI-X, PCI Express. In addition, the candidate should have strong experience in Object-oriented programming techniques. Excellent oral/written communication skills are a must.
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